The present invention relates to a method of fabricating a capacitor of a semiconductor device, and more particularly, to a method of fabricating a fin-shaped capacitor having a fin-shaped electrode and a high dielectric layer.
With the increase of integration of a dynamic random access memory (DRAM) device, a number of methods have been proposed to increase a capacitance within a limited cell area. Generally, these methods are classified into the following three methods: (1) making a dielectric layer thinner, (2) increasing an effective area of the capacitor, and (3) using a material for the dielectric layer having a high dielectric constant.
The first method has the drawback that it cannot be applied to a memory device of very large capacity. Since reliability is lowered by a Fowler-Nordheim current when the thickness of a dielectric layer is thinned to below 100 .ANG., the first method is limited to memory devices whose dielectric layer has a thickness greater than 100 .ANG.. Thus, any large capacity memory device requiring a dielectric layer thinner than 100 .ANG. can not be constructed using the first method.
Accordingly, the second method has been proposed using capacitors having three dimensional structures such as a cylinder shape or a fin shape. These shapes serve to increase the effective area of the capacitor, without reducing the thickness of the dielectric layer below its minimum thickness.
In addition, new materials for the dielectric layer have been proposed having high dielectric constants. This also raises the capacitance of a capacitor without requiring that the thickness of the dielectric layer be reduced to a fatally low level. Materials currently used as dielectric layers include a ferroelectric material of a perovskite structure, for example, BZT (PbZrTiO.sub.2) or BST (BaSrTiO.sub.3), and another materials having high dielectric constants, such as tantalum pentoxide (Ta.sub.2 O.sub.5).
The ferroelectric material has a spontaneous polarization which is different from a conventional oxide layer and the dielectric constant of the ferroelectric material ranges from about several hundreds up to one thousand. When using such a ferroelectric material as a dielectric layer, it is possible to realize a thin equivalent oxide thickness of less than 10 .ANG. by using the ferroelectric material layer having thickness of several hundreds of angstroms. Tantalum pentoxide has a dielectric constant three times the that of a silicon oxide or silicon nitride and has been widely researched as a desirable dielectric layer for a high integration DRAM.
In order to use the PZT or the BST as the dielectric layer, the material constituting the electrode of the capacitor must satisfy the following conditions. First, since a high temperature, above 800.degree. C., is needed for the dielectric layer to form on a surface of an electrode as a perovskite structure, the electrode material must be stable at high temperatures. Second, a layer having a low dielectric constant should not be generated on an interface between the electrode and the ferroelectric. Third, the mutual diffusion of atoms constituting silicon or ferroelectric should be prevented. Fourth, a patterning of the electrode should be easily accomplished.
Currently, platinum (Pt) is most frequently used as the electrode material for a capacitor using a ferroelectric material such as PZT or BST in its dielectric layer. Platinum satisfies the first, second, and third conditions, but does not satisfy the fourth condition. Generally, it is difficult to etch a noble metal such as platinum so that the patterning of a platinum electrode is not easy. Therefore, a material containing ruthenium (Ru) has been proposed as the electrode of a capacitor using PZT or BST as its dielectric material. This is shown, for example, in U.S. Pat. No. 5,185,689. However, since the prior art electrode is of plate shape, a problem arises in that the effective area of the capacitor is limited to the area of the plate.
FIG. 1 is a cross-sectional view of a memory cell having a ferroelectric capacitor manufactured according to the above conventional method. Referring to FIG. 1, a transistor is formed on a substrate 10 by first providing a gate oxide layer 14 and a gate electrode 16 above the gate oxide layer 14. A drain region 18a and a source region 18b are then created on the substrate on either side of the gate electrode 16, and a lower bit line 20 is formed above the drain region 18a. A field oxide layer 12, defining an active region, is then formed on the substrate 10 and an insulating layer 23 is formed on the whole surface of the resultant structure.
Next, a contact hole for exposing source region 18b is formed in the insulating layer 23 and the inside of the contact hole is filled with a conductive material to form a conductive plug 22. Then, a diffusion barrier 24 and a lower electrode 26 of the capacitor, composed of platinum (Pt), are sequentially formed on the resultant structure and an oxide spacer 28 is formed on the side walls of the lower electrode 26. A ferroelectric layer 30 composed of BST, an upper electrode 32 of the capacitor, an upper bit line 34, and an Al wiring 36 are then formed sequentially above the lower electrode 26.
When forming a storage node according to the above conventional method the potential increase in the area of the capacitor is limited since only the flat surface of the storage electrode can be used. Since the material used as the lower electrode 26 in the conventional ferroelectric capacitor cannot be easily patterned, a more complicated structure such as a fin shape cannot be formed to increase the effective area of the capacitor.
An additional problem arises if tantalum pentoxide is used in the fabrication of the capacitor. When using tantalum pentoxide, the characteristics of the capacitor deteriorate because of a BPSG flow after the capacitor is formed.
A poly-Si/TiN/Ta.sub.2 O.sub.5 /poly-Si structure has been proposed as the electrode structure for preventing the deterioration of the capacitor consisting of the tantalum pentoxide in Kwon ki-won et al., "Degradation-Free Ta.sub.2 O.sub.5 Capacitor after BPSG Reflow at 850.degree. C. for High Density DRAMs" (IEDM 1993). However, since a sputtered TiN is used as an upper electrode in this case, the step coverage of TiN deteriorates if the storage node becomes complicated. Thus, the lower electrode of a complicated structure cannot be adopted in the conventional tantalum pentoxide capacitor.